AMD devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15 in 7 series devices, and bank 65 in the UltraScale architecture.
To support the appropriate configuration interface voltage on bank 0, the Configuration Bank Voltage Select pin (CFGBVS) must be set to VCCO_0 or GND to configure I/O Bank 0 for either 3.3V/2.5V or 1.8V/1.5V operation respectively. The CFGBVS is a logic input pin referenced between VCCO_0 and GND. When the CFGBVS pin is connected to the VCCO_0 supply, the I/O on bank 0 support operation at 3.3V or 2.5V during configuration. When the CFGBVS pin is connected to GND, the I/O in bank 0 support operation at 1.8V or 1.5V during configuration.
The CFGBVS pin setting determines the I/O voltage support for bank 0 at all times. For 7 series devices in which bank 14 and bank 15 are the HR bank type, or bank 65 in UltraScale architecture, the CFGBVS pin and the respective CONFIG_VOLTAGE property determine the I/O voltage support during configuration.
Refer to the 7 Series FPGAs Configuration User Guide (UG470), or the UltraScale Architecture Configuration User Guide (UG570) for more information on Configuration Bank Voltage Select.
The Report DRC command checks the CFGBVS and CONFIG_VOLTAGE properties to determine the compatibility of CONFIG_MODE setting on the current design.
Architecture Support
All architectures.
Applicable Objects
Designs (current_design)
Value
- VCCO
- Configure I/O Bank 0 for 3.3V/2.5V operation.
- GND
- Configure I/O Bank 0 for 1.8V/1.5V operation.
Syntax
- VHDL Syntax
-
Not applicable
- Verilog Syntax
-
Not applicable
- XDC Example Syntax
-
set_property CFGBVS [VCCO | GND] [current_design]XDC Syntax Example:
# Configure I/O Bank 0 for 3.3V/2.5V operation set_property CFGBVS VCCO [current_design]
Affected Steps
- I/O Planning
- Report DRC
- Write Bitstream