PROCESSING_ORDER - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The PROCESSING_ORDER property determines if an XDC file will be processed early by the Vivado Design Suite during constraint processing, or processed normally, or processed late. The PROCESSING_ORDER can be: EARLY, NORMAL, or LATE.

By default, the Vivado Design Suite reads XDC files for IP cores before the user XDC files defined in the constraint fileset for the top-level design. Processing constraints in this way allows an IP to define constraints required by the core, while letting you override those IP constraints with user constraints processed later. Refer to this link in the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.

The default processing order for constraint files is:

  1. User Constraints marked as EARLY
  2. IP Constraints marked as EARLY (default)
  3. User Constraints marked as NORMAL
  4. IP Constraints marked as LATE (contain clock dependencies)
  5. User Constraints marked as LATE

User constraint files marked with a common PROCESSING_ORDER will be processed in the order they are defined in a constraint set, as displayed in the Vivado IDE. The order of the files can be modified by changing the compile order of the files in the Vivado IDE, or by using the reorder_files command.

Architecture Support
All architectures.
Applicable Objects
Constraint Files, XDC or Tcl, (get_files)
Values
EARLY
Process these files before other constraint files.
NORMAL
Process these files after the EARLY files and before the LATE files (default).
LATE
Process these files after other constraint files.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property PROCESSING_ORDER {EARLY | NORMAL | LATE} [get_files <filename>]

Where <filename> is the filename of an XDC or Tcl constraints file.

XDC Syntax Example:

set_property PROCESSING_ORDER EARLY [get_files char_fifo_ooc.xdc]

Affected Steps

  • Synthesis
  • Implementation