DIFF_TERM - 2024.2 English - 2024.1 English

The differential termination (DIFF_TERM) property supports the differential I/O standards for inputs and bidirectional ports. It is used to enable or disable the built-in, 100Ω, differential termination. Refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.

DIFF_TERM indicates a differential termination method should be used on differential input and bidirectional port buffers, and that the Vivado tool should add on-chip termination to the port.

Architecture Support

7 series FPGAs.

Recommended: For UltraScale architecture devices, you should use DIFF_TERM_ADV to enable differential termination.

Applicable Objects

• Ports (get_ports)
  • Input or bidirectional ports connected to a differential input buffer
• Applicable to elements using one of the following IOSTANDARDs:
  • LVDS, LVDS_25, MINI_LVDS_25
  • PPDS_25
  • RSDS_25

Values

TRUE

Differential termination is enabled.

FALSE

Differential termination is disabled (default).

Syntax

Verilog Syntax

Assign the DIFF_TERM parameter immediately before the port declaration:

(* DIFF_TERM = "TRUE" *) input PORT

Verilog Example Syntax:

// Enables differential termination on the specified port 
(* DIFF_TERM = "TRUE" *) input CLK;

VHDL Syntax

Declare and specify the VHDL attribute as follows:

attribute DIFF_TERM : string;
attribute DIFF_TERM of port_name : signal is "TRUE";

VHDL Syntax Example

-- Designates differential termination on the specified port attribute 
DIFF_TERM of CLK : signal is "TRUE";

XDC Syntax

set_property DIFF_TERM TRUE [get_ports port_name]

Where:

• set_property DIFF_TERM can be assigned to port objects.
• port_name is an input or bidirectional port connected to a differential buffer.

XDC Syntax Example:

# Enables differential termination on port named CLK_p set_property DIFF_TERM TRUE [get_ports CLK_p]

Affected Steps

• I/O Planning
• report_ssn
• report_power