DELAY_BYPASS - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The DELAY_BYPASS property reduces the delay through the BUFIO in AMD 7 series FPGAs.

There is an intrinsic delay in the BUFIO to match the delay of the BUFR to allow for smooth data transference from those domains. For 7 series devices, this property disables that delay.

Architecture Support
7 series FPGAs.
Applicable Objects
BUFIO (get_cells)
Value
TRUE
Delay bypass is enabled.
FALSE
Delay bypass is disabled (default).

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property DELAY_BYPASS TRUE [get_cells <cells>]

Where <cells> is a list of BUFIO cells to bypass the intrinsic delay.

XDC Syntax Example

set_property -name DELAY_BYPASS TRUE [get_cells clk_bufio]

Affected Steps

  • Timing Analysis