U_SET - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

Groups design elements with attached Relative Location (RLOC) constraints that are distributed throughout the design hierarchy into a single set.

U_SET is an attribute within the HDL design source files, and does not appear in the synthesized or implemented design. U_SET is used when defining Relatively Placed Macros, or RPMs in the RTL design. For more information on using these properties, and defining RPMs, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).

While H_SET or HU_SET are used to define sets of logic elements based on the design hierarchy, you can manually create a User-defined set of logic elements, or U_SET, that is not dependent on the hierarchy of the design.

When RLOC is also present in the RTL source files, the H_SET, HU_SET, and U_SET properties get translated to a read-only RPM property on cells in the synthesized netlist. The HU_SET and U_SET property are visible on the RTL source file in the Text editor in the Vivado Design Suite. However, in the Properties window of a cell object, the RPM property is displayed.

Important: When attached to hierarchical modules, the U_SET constraint propagates downward through the hierarchy to any primitive symbols that are assigned RLOC constraints.
Architecture Support
All architectures.
Applicable Objects

The U_Set constraint can be used in one or more of the following design elements, or categories of design elements. Refer to the Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953) or the UltraScale Architecture Libraries Guide (UG974) for more information on the specific design elements:

  • Registers
  • Macro Instance
  • RAMS*
  • RAMD*
  • RAMB*
  • DSP48*
Values
<NAME>: A unique name for the U_SET.

Syntax

Verilog Syntax

This is a Verilog attribute used in combination with the RLOC property to define the set content of a hierarchical block that will define an RPM in the synthesized netlist. Place the Verilog attribute immediately before the instantiation of a logic element.

(* RLOC = "X0Y0", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));

Verilog Example:

The following Verilog module defines RLOC and U_SET properties for the shift register flops in the module.

module ffs ( input	clk, input	d, output q
);

wire sr_0, sr_0n; wire sr_1, sr_1n; wire sr_2, sr_2n; wire sr_3, sr_3n; wire sr_4, sr_4n; wire sr_5, sr_5n; wire sr_6, sr_6n; wire sr_7, sr_7n;

wire	inr, inrn, outr;

inv i0 (sr_0, sr_0n); inv i1 (sr_1, sr_1n); inv i2 (sr_2, sr_2n); inv i3 (sr_3, sr_3n); inv i4 (sr_4, sr_4n); inv i5 (sr_5, sr_5n); inv i6 (sr_6, sr_6n); inv i7 (sr_7, sr_7n); inv i8 (inr, inrn);

(* RLOC = "X0Y0", U_SET = "Uset0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
(* RLOC = "X0Y0", U_SET = "Uset0" *) FD sr1 (.C(clk), .D(sr_2n), .Q(sr_1));
(* RLOC = "X0Y1", U_SET = "Uset0" *) FD sr2 (.C(clk), .D(sr_3n), .Q(sr_2));
(* RLOC = "X0Y1", U_SET = "Uset0" *) FD sr3 (.C(clk), .D(sr_4n), .Q(sr_3));
(* RLOC = "X0Y0", U_SET = "Uset1" *) FD sr4 (.C(clk), .D(sr_5n), .Q(sr_4));
(* RLOC = "X0Y0", U_SET = "Uset1" *) FD sr5 (.C(clk), .D(sr_6n), .Q(sr_5));
(* RLOC = "X0Y1", U_SET = "Uset1" *) FD sr6 (.C(clk), .D(sr_7n), .Q(sr_6));
(* RLOC = "X0Y1", U_SET = "Uset1" *) FD sr7 (.C(clk), .D(inrn), .Q(sr_7));
 

(* LOC = "SLICE_X0Y0" *) FD inq (.C(clk), .D(d), .Q(inr));
FD outq (.C(clk), .D(sr_0n), .Q(outr)); assign q = outr;
endmodule // ffs

Unlike the HU_SET property, which applies to the level of hierarchy it is defined in, the U_SET property transcends hierarchy. In this case, the following top-level module defines three instances of the ffs module, but results in only two U_SETS being created: Uset_0 and Uset_1, which contain Flops from all three ffs module instances defined below:

module top ( input	clk, input	d, output q
);
wire	c1,  c2; ffs u0 (clk, d, c1);
ffs u1 (clk, c1, c2); ffs u2 (clk, c2, q);

endmodule // top
VHDL Syntax

Declare the VHDL attribute as follows:

attribute U_SET : string;

Specify the VHDL constraint as follows:

attribute U_SET of {component_name | entity_name | label_name} :
{component|entity|label} is "NAME";

Where:

  • {component_name | entity_name | label_name} is a choice of one design element.
  • {component | entity | label} is the instance ID of the design element.
  • "NAME" is the unique set name to give to the U_SET.
XDC Syntax

The U_SET property can not be defined using XDC constraints. The U_SET property, when present on logic elements with the RLOC property, defines relatively placed macros (RPMs), and results in the read-only RPM property in the netlist of synthesized designs.

Tip: You can use the create_macro and update_macro commands to define macro objects in the Vivado Design Suite, that act like RPMs within the design. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information on these commands.

Affected Steps

  • Design Floorplanning
  • Place Design
  • Synthesis