The IS_ENABLED property lets you enable or disable individual design rule checks (DRC) in the Vivado Design Suite when running Report DRC. For more information on Running DRCs, see this Vivado Design Suite User Guide: System-Level Design Entry (UG895).
You can enable or disable both built-in and custom DRCs. For information on writing custom design rule checks, see this Vivado Design Suite User Guide: Using Tcl Scripting (UG894).
To restore the DRC objects to the factory default setting, use the reset_drc_check Tcl command.
- Architecture Support
- All architectures.
- Applicable Objects
- Design Rule Check objects (
get_drc_checks)
- Values
-
-
TRUE: Enable the specified DRC for use during thereport_drccommand (default). -
FALSE: Disable the DRC so that the rule is not evaluated duringreport_drc.
-
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property IS_ENABLED {TRUE | FALSE} [get_drc_checks <id>]Where
<id>is the DRC ID recognized by the Vivado Design Suite.XDC Syntax Example:
set_property IS_ENABLED false [get_drc_checks RAMW-1]
Affected Steps
- report_drc
- Write Bitstream