IS_ENABLED - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The IS_ENABLED property lets you enable or disable individual design rule checks (DRC) in the Vivado Design Suite when running Report DRC. For more information on Running DRCs, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

You can enable or disable both built-in and custom DRCs. For information on writing custom design rule checks, see this link in the Vivado Design Suite User Guide: Using Tcl Scripting (UG894).

Important: Although Vivado allows you to disable and downgrade the severity of the built-in DRC Objects, this practice is highly discouraged as it can cause unpredictable results and could potentially cause permanent damage to the device.

To restore the DRC objects to the factory default setting, use the reset_drc_check Tcl command.

Architecture Support
All architectures.
Applicable Objects
Design Rule Check objects (get_drc_checks)
Values
  • TRUE: Enable the specified DRC for use during the report_drc command (default).
  • FALSE: Disable the DRC so that the rule is not evaluated during report_drc.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property IS_ENABLED {TRUE | FALSE} [get_drc_checks <id>]

Where <id> is the DRC ID recognized by the Vivado Design Suite.

XDC Syntax Example:

set_property IS_ENABLED false [get_drc_checks RAMW-1]

Affected Steps

  • report_drc
  • Write Bitstream