CELL_BLOAT_FACTOR - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The CELL_BLOAT_FACTOR property lets you specify the addition of “whitespace” or increased cell spacing to increase placement distance between the cells of a hierarchical module. The Vivado placer will space out the cells in the module to improve routing results of the design.

You can use cell bloating, when the placement of cells from a module is close together and causing congestion, to insert whitespace during the placement step. This leads to a lower density of cells in a given area of the die, which can reduce congestion by increasing available routing resources. This technique is particularly effective in small, congested areas of relatively high-performance logic.

Tip: The unused logic between cells of a module can be used by the Vivado placer for other cells that are not contained in the hierarchical module.

To use cell bloating, apply the CELL_BLOAT_FACTOR property to cells and set the value to LOW, MEDIUM, or HIGH.

HIGH is the recommended setting when working with smaller modules of several hundred cells. Using cell bloating on larger modules might force the placed cells of the module to be too far apart.

Important: If the device already uses too many routing resources, cell bloating is not recommended.

Architecture Support

All architectures.

Applicable Objects

Cells (get_cells)

Value

LOW | MEDIUM | HIGH: Specifies the relative spacing between the cells of an hierarchical module.

Tip: The property can be applied to both hierarchical and leaf level cells. However, it is recommended to apply the property to hierarchical cells ONLY for better compile time and memory consumption.

Syntax

VHDL Syntax

Not applicable

Verilog Syntax

Not applicable

XDC Syntax
set_property CELL_BLOAT_FACTOR <value> <objects>

XDC Syntax Example:

The following assigns a CELL_BLOAT_FACTOR property to the cpuEngine module:

set_property CELL_BLOAT_FACTOR high [get_cells { cpuEngine }]

Affected Steps

  • Place Design
  • Routing (Route Design)