IBUF_LOW_PWR - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

The IBUF_LOW_PWR property allows an optional trade-off between performance and power.

The IBUF_LOW_PWR property is applied to an input port. This property is set to TRUE by default, which implements the input buffer for the port in the lower-power mode rather than the higher-performance mode (FALSE).

The change in power can be estimated using the Xilinx Power Estimator (XPE) or the report_power command in the Vivado Design Suite.

Architecture Support
All architectures
Applicable Objects
Input ports (get_ports) with a VREF-based I/O Standard such as SSTL or HSTL or a differential standard such as LVDS or DIFF_HSTL.
Values
  • TRUE: Implements the input or bidirectional buffer for the port in low power mode. This is the default value.
  • FALSE: Implements the input or bidirectional buffer in high performance mode.

Syntax

Verilog Syntax

For both inferred and instantiated input and bidirectional buffers, place the proper Verilog parameter syntax before the top-level port declaration.

(* IBUF_LOW_PWR = "FALSE" *)

Verilog Syntax Example

// Sets the input buffer to high performance 
(* IBUF_LOW_PWR = "FALSE" *) input STATE,
VHDL Syntax

For both inferred and instantiated input buffers, place the proper VHDL attribute syntax before the top-level port declaration.

Declare and specify the VHDL attribute as follows:

attribute IBUF_LOW_PWR : boolean;
attribute IBUF_LOW_PWR of port_name : signal is TRUE | FALSE;

Where port_name is a top-level port.

VHDL Syntax Example:

STATE : in std_logic;
attribute IBUF_LOW_PWR : boolean;
-- Sets the input buffer to high performance attribute IBUF_LOW_PWR of STATE : signal is FALSE;
XDC Syntax

IBUF_LOW_PWR can be assigned as a property on port objects with a DIRECTION of IN or INOUT.

set_property IBUF_LOW_PWR TRUE [get_ports port_name]

Where:

  • set_property IBUF_LOW_PWR can be assigned to port objects.
  • port_name is an input or bidirectional port.

Affected Steps

  • report_power
  • report_timing