ASYNC_REG - 2024.2 English

Important: If ASYNC_REG and IOB are both assigned to a register, the IOB property takes precedence over ASYNC_REG and the register is placed in an ILOGIC block rather than into SLICE/CLB logic.

ASYNC_REG is an attribute that affects many processes in the Vivado tools flow. ASYNC_REG specifies that:

A register can receive asynchronous data on the D input pin relative to its source clock.
A register is a synchronizing register within a synchronization chain.

Figure 1. Synchronizing Clock Domains

During simulation, when a timing violation occurs, the default behavior is for a register element to output an 'X', or unknown state (not a 1 or 0). When this happens, anything that element drives will see an 'X' on its input and in turn enters an unknown state. This condition can propagate through the design, in some cases causing large sections of the design to become unknown, and sometimes the simulator can not recover from this state. ASYNC_REG modifies the register to output the last known value even though a timing violation occurs.

Vivado synthesis treats the ASYNC_REG property like the DONT_TOUCH property, and pushes it forward in the synthesized netlist. This ensures that synthesis will not optimize registers or surrounding logic, and that downstream tools in the design flow receive the ASYNC_REG property for processing.

Specifying ASYNC_REG also affects optimization, placement, and routing to improve mean time between failure (MTBF) for registers that can go metastable. If ASYNC_REG is applied, the placer will ensure the flip-flops on a synchronization chain are placed closely together to maximize MTBF. Registers that have this property that are directly connected will be grouped and placed together into a single SLICE/CLB, assuming they have a compatible control set and the number of registers does not exceed the available resources of the SLICE/CLB.

Note: For UltraScale devices, mean time between failures (MTBF) can be reported for synchronizing registers identified with ASYNC_REG using the report_synchronizer_mtbf command.

The following is a Verilog example of a two FF, or one-stage synchronizer, as shown in the preceding figure. The registers synchronize a signal from a separate clock domain. The ASYNC_REG property is attached to synchronizing stages with a value of TRUE:

(* ASYNC_REG = "TRUE" *) reg sync_0, sync_1; 
always @(posedge clk) begin
sync_1 <= sync_0; 
sync_0 <= en;
. . .

Tip: The ASYNC_REG property can also be used with SystemVerilog logic syntax:

(* ASYNC_REG =
					"TRUE" *) logic sync_0, sync_1;

-or-

(*
					ASYNC_REG = "TRUE" *) output logic sync_0, sync_1,

.

With the ASYNC_REG property, the registers are grouped so that they are placed as closely together as possible.

Figure 2. Grouping Registers

Architecture Support

All architectures.

Applicable Objects

Signals declared in the source RTL
Instantiated register cells (get_cells)
- Registers (FD, FDCE, FDPE, FDRE, FDSE)

Values

TRUE: The register is part of a synchronization chain. It will be preserved through implementation, placed near the other registers in the chain and used for MTBF reporting.
FALSE: The register can be optimized away, or absorbed into a block such as SRL, DSP, or RAMB. No special simulation, placement, or routing rules will be applied to it (default).

Syntax

Verilog Syntax

Place the Verilog attribute immediately before the instantiation or reg declaration of a register:

(* ASYNC_REG = "{TRUE|FALSE}" *)

Verilog Syntax Example

// Designates sync_regs as receiving asynchronous data 
(* ASYNC_REG = "TRUE" *) reg [2:0] sync_regs;

VHDL Syntax

Declare and specify the VHDL attribute as follows for inferred logic:

attribute ASYNC_REG : string;
attribute ASYNC_REG of name: signal is "TRUE";

Or, specify the VHDL attribute as follows for instantiated logic:

attribute ASYNC_REG of
							name: label is "TRUE";

Where name is the declared signal that will be inferred to a synchronizer register, or the instance name of an instantiated register.

VHDL Syntax Example:

attribute ASYNC_REG : string;
signal sync_regs : std_logic_vector(2 downto 1);
-- Designates sync_regs as receiving asynchronous data attribute ASYNC_REG of sync_regs: signal is "TRUE";

XDC Syntax

set_property ASYNC_REG value [get_cells <instance_name>]

Where <instance_name> is a register cell.

XDC Syntax Example


# Designates sync_regs as receiving asynchronous data set_property 
ASYNC_REG TRUE [get_cells sync_regs*]

Affected Steps

launch_xsim
Synthesis
Place Design
Route Design
Phys Opt Design
Power Opt Design
report_drc
write_verilog
write_vhdl