The core is delivered through the Vivado Design Suite with an HDL example design built around the core which when placed on a suitable board allows the functionality of the core to be demonstrated using either a simulation package or in hardware. The following figure shows a block diagram of the example design. For details about the Vivado example design, see Example Design.
The example design shows how to:
- Instantiate the core from HDL.
- Source and use the user-side interface ports of the core from application logic.
- Connect the physical-side interface of the core (GMII/MII or RGMII) to device IOBs creating an external interface. (See the Physical Interface chapters in this document)
- Derive the clock logic required for the core (See the Physical Interface sections in this document).
Figure 1. Tri-Mode Ethernet MAC Core Example Design
Using the example design as a starting point enables you to do the following:
- Edit the HDL top-level of the example
design file to:
- Change the clocking scheme.
- Add/remove IOBs as required.
- Replace the basic pattern generator logic with your specific application logic.
- Adapt the 10 Mbps, 100 Mbps, and 1 Gbps Ethernet FIFO to suit your specific application (see 10, 100, 1000 Mbps Ethernet FIFO).
- Remove the AXI4-Lite Control State machine and directly drive the AXI4-Lite bus from a processor.
- Synthesize the entire design.
- Implement the entire design.
- After the completion of implementation you can also create a bitstream that can be downloaded to an AMD device.
- Simulate the entire design using the provided demonstration test bench.
- Download the bitstream to a target device.