HR I/O do not include ODELAY components and another method is required to introduce the required 2 ns offset between the clock and data.
The logic required to implement the
RGMII transmitter logic is illustrated in the following figure . The gtx_clk and gtx_clk90 signals
are 125 MHz reference clock sources with 0ο and 90ο phase shift respectively. These can be created using an MMCM
driving BUFGs and as illustrated, this clocking logic can be provided in the core by the
Shared Logic option. The gtx_clk is used as the clock for the
RGMII data and control. It is used both within the core and for the user-side logic which
connects to the transmitter AXI4-Stream interface of the core. The gtx_clk90 is used only for the RGMII clock.
The following figure shows how to use the physical transmitter interface of the core to create an external RGMII. The signal names and logic shown in this figure exactly match those delivered with the core. The following figure shows that the output transmitter signals are registered in device IOBs using DDR registers, before driving them to the device pads.
The logic required to forward the
transmitter clock is also shown. This logic uses an IOB output
Double-Data-Rate (DDR) register so that the clock signal produced
incurs the same delay as the data and control signals. However, the
clock signal uses the 90ο phase
shifted version of the clock. The result of this is to create a 2
ns delay, which places the rgmii_txc
forwarded clock in the center of the data valid window for
forwarded RGMII data and control signals.
