The following table describes the optional signals that you used to access the Ethernet MAC core level, including configuration, status, and MDIO access. See Management Interface.
Note: The bus width of the write and read addresses depends on whether
AVB endpoint is enabled or disabled.
| Signal | Direction | Clock Domain | Description |
|---|---|---|---|
| s_axi_aclk | In | N/A | Clock for AXI4-Lite |
| s_axi_resetn | In | s_axi_aclk | Local reset for the clock domain |
| s_axi_awaddr[16:0] | In | s_axi_aclk |
Write Address When AVB endpoint is enabled. |
| s_axi_awaddr[11:0] | In | s_axi_aclk |
Write Address When AVB endpoint is disabled. |
| s_axi_awvalid | In | s_axi_aclk | Write Address Valid |
| s_axi_awready | Out | s_axi_aclk | Write Address Ready |
| s_axi_wdata[31:0] | In | s_axi_aclk | Write Data |
| s_axi_wvalid | In | s_axi_aclk | Write Data Valid |
| s_axi_wready | Out | s_axi_aclk | Write Data Ready |
| s_axi_bresp[1:0] | Out | s_axi_aclk | Write Response |
| s_axi_bvalid | Out | s_axi_aclk | Write Response Valid |
| s_axi_bready | In | s_axi_aclk | Write Response Ready |
| s_axi_araddr[16:0] | In | s_axi_aclk |
Read Address When AVB endpoint is enabled. |
| s_axi_araddr[11:0] | In | s_axi_aclk |
Read Address When AVB endpoint is disabled. |
| s_axi_arvalid | In | s_axi_aclk | Read Address Valid |
| s_axi_arready | Out | s_axi_aclk | Read Address Ready |
| s_axi_rdata[31:0] | Out | s_axi_aclk | Read Data |
| s_axi_rresp[1:0] | Out | s_axi_aclk | Read Response |
| s_axi_rvalid | Out | s_axi_aclk | Read Data/Response Valid |
| s_axi_rready | In | s_axi_aclk | Read Data/Response Ready |