Configuration Vector Signal Definition - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
Document ID
PG051
Release Date
2023-11-07
Version
9.0 English

The following table describes the configuration vectors that use direct inputs to the core to replace the functionality of the MAC configuration bits when the Management Interface is not used. The configuration settings described in Table 2to Table 8 are included in the vector.

Table 1. Alternative to Optional Management Interface – Configuration Vector Signal Pinout
Signal Direction Clock Domain Description
rx_configuration_vector[79:0] 2 In rx_mac_aclk The RX Configuration Vector is used to replace the functionality of the MAC RX Configuration registers when the Management interface is not used.
tx_configuration_vector[79:0] 3 In tx_mac_aclk The TX Configuration Vector is used to replace the functionality of the MAC TX Configuration registers when the Management interface is not used.
  1. All bits of the config vectors are registered on input but can be treated as asynchronous inputs.
  2. When PFC is enabled rx_configuration_vector has a bus width of Bits[95:0].
  3. When PFC is enabled tx_configuration_vector has a bus width of Bits[367:0].