Pattern Generator - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

This pattern generator can be enabled/disabled using a DIP switch. When enabled, the data from the RX FIFO is flushed and the axi_pat_gen_2g5 module drives the tx_client_fifo_2g5 module inputs.

The pattern generator allows user modification of the Destination Address, Source Address, minimum frame size, and maximum frame size using parameters. When enabled, using a dedicated input mapped to a DIP switch on a board, it starts with the minimum frame size and after each frame is sent, increments the frame size until the maximum value is reached, it then starts again at the minimum frame size.

In all cases, the Destination and Source address are as provided by HDL parameters, with the Type/Length field being dependent upon the frame size and the frame data being an incrementing count starting from 0x0. The payload value increment across successive frames and rolls over when it is 0xFF.