RGMII - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The logic required to implement the RGMII transmitter logic is illustrated in Figure 1. The gtx_clk is a user-supplied 125 MHz reference clock source which is placed onto global clock routing. It provides the clock for all transmitter logic within the core, and for the user-side logic which connects to the transmitter AXI4-Stream interface of the TEMAC.

For RGMII, this global 125 MHz is used to clock transmitter logic at all three Ethernet speeds. The data rate difference between the three speeds is compensated for by the transmitter clock enable logic (the enable_gen module from the example design describes the required logic). The derived tx_enable signal must be supplied to the Ethernet MAC core level. All user logic uses the AXI4-Stream interfaces built in handshaking to throttle the data appropriately, under control of the Ethernet MAC core level. At all speeds the MAC expects the user logic to supply/accept new data after each validated clock cycle. The generated tx_enable signal is always High at 1 Gbps, High for one in ten cycles at 100 Mbps, and High for one in a hundred cycles at 10 Mbps. The advantage of this approach is that it allows common transmitter global clocks to be shared across any number of instantiated cores.

Figure 1 illustrates how to use the physical transmitter interface of the core to create an external RGMII. The signal names and logic shown in this figure exactly match those delivered with the core. Figure 1 shows that the output transmitter signals are registered in byte slice, using DDR registers, before driving them to the device pads.

The logic required to forward the transmitter clock is also shown. This logic uses a byte slice Output Double-Data-Rate (DDR) register so that the clock signal produced incurs exactly the same delay as the data and control signals. However, the clock signal is then routed through an output delay element (ODELAY cascaded with IDELAY) before connecting to the device pad. The result of this is to create a 2 ns delay, which places the rgmii_txc forwarded clock in the center of the data valid window for forwarded RGMII data and control signals when operating at 1 Gbps Ethernet speed. At 10 Mbps and 100 Mbps speeds, the enable_gen module toggles the DDR input signals at the required frequency so that the forwarded rgmii_txc clock is always of the correct frequency for the forwarded data.

TXC cannot be placed at BITSLICE0 of the lower nibble. This is because TXC is routed through a delay chain consisting of ODELAY cascaded with IDELAY. Given that, cascading always happens in a downward direction, until the byte boundary. TXC placed at BITSLICE0 of the lower nibble cannot be cascaded with IDELAY.

RX Data/Control pins or any input pin which needs to be routed through IDELAY cannot be placed at BITSLICE below TXC. This is because of the cascaded delay chain on TXC which occupies the IDELAY of the lower BITSLICE.

For further information, see UltraScale Architecture Clocking Resources User Guide (UG572).

For UltraScale+ devices, RGMII interface logic uses only the IDELAY/ODELAY components to provide skew between clock and data lines. This requirement restricts you from placing the RGMII interface pins in HD I/O banks as these banks do not have any IDELAY/ODELAY elements.