MII Receiver Interface - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The logic required to implement the MII receiver logic is also illustrated in Figure 1. mii_rx_clk is provided by the external PHY device connected to the MII. As illustrated, this is placed onto global clock routing (BUFG) to provide the clock for all receiver logic, both within the core and for the user-side logic which connects to the RX AXI4-Stream interface of the TEMAC.

To match the user data rate, which uses an 8-bit datapath and the MII, which uses a 4-bit datapath, the RX AXI4-Stream interface is throttled, using rx_axis_mac_tvalid, under control of the MAC to limit data transfers to every other cycle. Figure 1 also illustrates how to use the physical receiver interface of the core to create an external MII. The signal names and logic shown in this figure exactly match those delivered with the example design. Figure 1 shows that the input receiver signals are registered in device IOBs before routing them to the core.