Low-Frequency Statistical Counters - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The increment_vector[4:43] is an input bus signal which provides the predefined counters as described in Table 1 and three user-defined counters.

This accommodates the majority of the statistical counters that only increment at (or less frequently than) a minimum Ethernet frame period.

The following figure illustrates the increment_vector bus provided by the vector decode block. There is an increment bit for each counter from counter four upwards. A toggle on a particular increment bit causes the corresponding counter to increment. The mapping of the increment vector bits to the various register-mapped counter is shown in Table 1.

Figure 1. Increment Vector Timing Diagram

The increment_vector is input to the core, and edge detection circuitry (toggle detection) is placed on each bit. The toggle detection circuitry is synchronous to stats_ref_clk . The distributed memory stores the current counter values within the core. The Statistics core accesses each of the counters within this memory in a round-robin fashion. If an increment is requested because, in the last access, the relative value is incremented before being written back to memory.