Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051) - 9.0 English - Describes the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC, and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation. - PG051
Document ID
PG051
Release Date
2024-12-11
Version
9.0 English
Introduction
Features
IP Facts
Overview
Core Overview
Recommended Design Experience
Ethernet Overview
MAC
GMII/MII
RGMII
SGMII
PCS, PMA, and PMD
Core Overview
Ethernet MAC Core
AXI4-Lite Wrapper
Statistics Vector Decode
PHY Interface
Ethernet AVB Endpoint
Precise Timing Protocol (PTP)
TX Arbiter
Transmit Engine
Receive Engine
Flow Control
GMII/MII Block
Management Interface
MDIO Interface
Frame Filter
Ethernet Communications Port for an Embedded Processor
Statistics Counters
Feature Summary
Applications
Ethernet Switch or Router
Ethernet AVB Endpoint System
Licensing and Ordering
License Checkers
Product Specification
Standards
Performance
Latency
Receive Path Latency
Transmit Path Latency
Resource Utilization
Port Descriptions
User Interfaces
Transmitter Interface
Receiver Interface
Flow Control Interface (IEEE 802.3)
Priority Flow Control Interface (802.1Qbb)
AXI4-Lite Signal Definition
Configuration Vector Signal Definition
Clock, Speed Indication, and Reset Signal Definition
Interrupt Signals
Ethernet AVB Endpoint PTP Signals
Physical Interface Signals
MDIO Signal Definition
PHY Interface Signal Definition
I/O Delay Calibration Ports for TEMAC RGMII Interface
Configuration Vector
Register Space
Statistics Counters
MAC Configuration Registers
ID Register (0x4F8)
MDIO
MDIO Configuration Registers
Interrupt Controller
Frame Filter Configuration
AVB Specific Frame Filters
PTP Frame Filter
SR Classes A and B Frame Filters
AVB Endpoint
RX PTP Packet Buffer Address Space
TX PTP Packet Buffer Address Space
AVB Configuration
AVB Configuration Registers
TX PTP Packet Buffer Control Register
RX PTP Packet Buffer Control Register
TX Arbiter Send Slope Control Register
TX Arbiter Idle Slope Control Register
RTC Configuration
RTC Nanoseconds Field Offset Control
RTC Seconds Field Offset Control
RTC Increment Value Control Register
Current RTC Value Registers
RTC Interrupt Clear Register
RTC Phase Adjustment Register
System Requirements
Designing with the Core
General Design Guidelines
Design Steps
Using the Example Design as a Starting Point
Implementing the Tri-Mode Ethernet MAC
Keep it Registered
Recognize Timing Critical Signals
Make Only Allowed Modifications
Shared Logic
RGMII for 7 Series Devices
GMII for 7 Series Devices
MII or Internal Interface for 7 Series Devices
GMII/RGMII for UltraScale Devices
MII or Internal Interface for UltraScale Devices
Clocking
Resets
Protocol Description
Ethernet Sublayer Architecture
MAC and MAC CONTROL Sublayer
Physical Sublayers PCS, PMA, and PMD
Ethernet Data Format
Preamble
Start of Frame Delimiter
MAC Address Fields
MAC Address
Destination Address
Source Address
Length/Type
Data
Pad
FCS
Frame Transmission and Interframe Gap
Half-Duplex Frame Transmission
Full-Duplex Frame Transmission
AXI4-Stream User Interface
Receiving Inbound Frames
Normal Frame Reception
rx_axis_mac_tlast and rx_axis_mac_tuser Timing
Frame Reception with Errors
User-Supplied FCS Passing
VLAN Tagged Frames
Maximum Permitted Frame Length
Length/Type Field Error Checks
Frame Filter
Receive Statistics Vector
Transmitting Outbound Frames
Normal Frame Transmission
Padding
User-Supplied FCS Passing
User Error Indication
Back-to-Back Transfers
VLAN Tagged Frames
Maximum Permitted Frame Length
Frame Collisions – Half-Duplex Operation Only
Interframe Gap Adjustment – Full-Duplex Mode Only
Transmit Statistics Vector
Flow Control Using IEEE 802.3
Flow Control Overview
Flow Control Basics
Pause Control Frames
Flow Control Operation of the TEMAC
Transmitting a Pause Control Frame
Core-Initiated Pause Request
User-Initiated Pause Request
XON/XOFF Extended Functionality
Receiving a Pause Control Frame
Core-Initiated Response to a Pause Request
Pause Frame Reception Disabled
Pause Frame Reception Enabled
User-Initiated Response to a Pause Request
Flow Control Implementation Example
Method
Operation
Using Priority Flow Control
Priority Flow Control Requirement
Priority-Based Flow Control Frames
Transmitting a PFC Frame
Core-Initiated Request
Client-Initiated Request
Receiving a PFC Frame
Core-Initiated Response to a PFC request
PFC Frame Reception Disabled
Pause Frame Reception Enabled
Client-Initiated Response to a Pause Request
PFC Implementation Example
Method
Operation
Statistics Counters
Increment Interface Overview
Low-Frequency Statistical Counters
Bandwidth Requirements
Frame Filter
Using the Frame Filter
Frame Filter Example Application
Using the AVB Specific Frame Filters
SR Classes A and B Frame Filters
Ethernet AVB Endpoint
Ethernet AVB Endpoint Transmission
TX Legacy Traffic Interface
TX AV Traffic Interface
Transmitter AXI4-Stream AV Specifics
TX Arbiter
Overview
Credit-Based Traffic Shaping Algorithm
TX Arbiter Bandwidth Control
idleSlope
sendSlope
Ethernet AVB Endpoint Reception
RX Legacy Traffic Interface
RX AV Traffic Interface
Real-Time Clock and Timestamping
Real-Time Clock
RTC Implementation
Increment of Nanoseconds Field
Increment of the Seconds Field
Clock Outputs Based on the Synchronized RTC Nanoseconds Field
Timestamping Logic
Timestamp Sampling Position of MAC Frames
IEEE1722 Real-Time Clock Format
Precise Timing Protocol Packet Buffers
TX PTP Packet Buffer
RX PTP Packet Buffer
Configuration and Status
Management Interface
Address Map
MAC Configuration
MDIO Interface
MDIO Bus System
MDIO Transactions
MDIO Port Options
Connecting the MDIO to an Internally Integrated PHY
Connecting the MDIO to an External PHY
Connecting the MDIO to an External and Internal PHY
Accessing PHY Configuration Registers, through MDIO Using the Management Interface
MDIO Configuration and Control
Interrupt Controller
Configuration Vector
Frame Filter
TEMAC Configuration Settings
Half-Duplex Configuration Settings
Half-Duplex and Flow Control Configuration Settings
MAC Address Settings
AVB Endpoint
Physical Interface for 7 Series and Zynq 7000 Devices
10 or 100 Mbps Ethernet MAC Core Interfaces
MII Transmitter Interface
MII Receiver Interface
Multiple Core Instances with the MII
1 Gbps Ethernet MAC Core Interfaces
GMII Transmitter Interface
GMII Receive Interface
IDELAYCTRL
Clock Sharing across Multiple Cores with GMII for 1 Gbps Operation
RGMII
IDELAYCTRL
Transmitter Logic for 7 Series Using HR I/O
Receiver Logic
IDELAYCTRL
Clock Resource Sharing across Multiple Cores with RGMII for 1 Gbps Operation
Tri-Speed Ethernet MAC Core Interfaces
GMII Transmitter Interface
GMII Receive Interface
IDELAYCTRL
Clock Resource Sharing across Multiple Cores with GMII for Tri-Speed Operation
RGMII
IDELAYCTRL
Receiver Logic
Clock Resource Sharing across Multiple Cores with RGMII for Tri-Speed Operation
Physical Interface for UltraScale Devices
10 or 100 Mbps Ethernet MAC Core Interfaces
MII Transmitter Interface
MII Receiver Interface
Multiple Core Instances with the MII
1 Gbps Ethernet MAC Core Interfaces
GMII Transmitter Interface
GMII Receive Interface
IDELAYCTRL
Clock Sharing across Multiple Cores with GMII for 1 Gbps Operation
RGMII
IDELAYCTRL
Receiver Logic
IDELAYCTRL
Clock Sharing across Multiple Cores with RGMII for 1 Gbps Operation
Tri-Speed Ethernet MAC Core Interfaces
GMII Transmitter Interface
GMII Receive Interface
IDELAYCTRL
Clock Sharing across Multiple Cores with GMII for Tri-Speed Operation
RGMII
IDELAYCTRL
Receiver Logic
Clock Sharing across Multiple Cores with RGMII for Tri-Speed Operation
Interfacing to Other AMD Ethernet Cores
Ethernet 1G/2.5G PCS/PMA or SGMII Core
Design Flow Steps
Customizing and Generating the Core
Data Rate
Component Name
Physical Interface
MAC Speed
Internal Mode Clock Source
Management Type
AXI4-Lite Frequency
Shared Logic
MAC Options
AVB Option
Frame Filter Options
Number of Table Entries
Enable Priority Flow Control
Statistics Counters
Statistics Width
Statistics Reset
Board
User Parameters
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
I/O Standard and Placement
IDELAYCTRL
7 Series Devices
UltraScale Devices
Simulation
Synthesis and Implementation
Example Design
10, 100, 1000 Mbps Ethernet FIFO
rx_client_fifo
tx_client_fifo
2.5 Gbps Ethernet FIFO
rx_client_fifo_2g5
tx_client_fifo_2g5
Basic Pattern Generator Module for 10, 100, 1000 Mbps Data Rates
Address Swap
Pattern Generator
Pattern Checker
Basic Pattern Generator Module for 2.5 Gbps Data Rate
Pattern Generator
Pattern Checker
AXI4-Lite Control State Machine
Targeting the Example Design to a Board
TEMAC Solution Configurations Supported
Bring-Up Sequence
KC705 Board
AC701 Board
Test Bench
Test Bench Functionality
Core with Management Interface
DEMO Mode
DEMO Mode with Frame Filter
BIST Mode
Core with No Management Interface
DEMO Mode
BIST Mode
Changing the Test Bench
DEMO Mode
Changing Frame Data
Changing Frame Error Status
BIST Mode
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Shared Logic
Port Additions in v9.0 Rev 4
Port Changes from v8.3 to v9.0
Ports Removed
Other Changes from v8.3 to v9.0
Shared Logic for UltraScale Architecture Devices
Port Changes from v8.2 to v8.3
Other Changes from v8.2 to v8.3
MDIO Logic
MDIO Interface
Port Changes from v8.1 to v8.2
Ports Added
Ports Removed
Other Changes from v8.1 to v8.2
IDLEAYCTRL
Number of Filter Table Entries
Port Changes from v8.0 to v8.1
Port Changes from v7.0 to v8.0
Ports Added
Ports Removed
Other Changes from v7.0 to v8.0
IDELAYCTRL
IP Upgrade
Calculating the MMCM Phase Shift or IODelay Tap Setting
MMCM Usage
MMCM Phase Shifting Requirements
Finding the Ideal Phase Shift Value
IODelay Usage
IODelay Tap Setting Requirements
Finding the Ideal Tap Setting Value
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Compiling Simulation Libraries
AMD Simulation Library Compilation Wizard
Implementation and Timing Errors
Regional Clocking Errors
Timing Failed for GMII/RGMII/MII OFFSET IN Constraint
Timing Violations on I/O Paths in GMII/RGMII – UltraScale Architecture Devices
Hardware Debug
General Checks
Problems with Transmitting and Receiving Frames
Issues with the MDIO
Configuring the Ethernet MAC to the Correct Speed
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices