Because both mii_tx_clk and gmii_rx_clk are sourced by the external
PHY device connected to the GMII/MII, it is not possible to share global transmitter or
receiver clock resources across multiple instantiations of the core. Each instance of the
core requires its own endpoint clocking resources. RGMII provides a more optimal solution
because it does allow transmitter clock resources to be shared. See RGMII.
The following figure illustrates that the upper core instance has been generated with the Shared Logic option enabled. For the GMII, this instantiates an IDELAYCTRL as illustrated. The other core instances have been generated without the Shared Logic option enabled (because only a single instance of an IDELAYCTRL is usually required per design). The following figure illustrates three cores. However, more can be added using the same principle. This is done by instantiating further cores without the Shared Logic option.
If the GTX clock (gtx_clk ) is sourced from a BUFG then it should be connected to multiple instances
of the TEMAC IP, using multiple BUFGs, as shown in the following figure . This is required to
limit the quantity of BUFGs are cascaded together up to two. For more details, see the
7
Series FPGAs Clocking Resources User Guide (UG472).
