MDIO Configuration Registers - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID: PG051
Release Date: 2023-11-07
Version: 9.0 English

Table 1. MDIO Configuration Registers
Address (Hex)	Description
0x500	Table 2
0x504	Table 3
0x508	Table 4
0x50C	Table 5

The contents of each configuration register are shown in the following tables.

Table 2. MDIO Setup Word (0x500)
Bits	Default Value	Type	Description
31:7	N/A	RO	Reserved
6	0x0	R/W	MDIO Enable: When this bit is 1, the MDIO interface can be used to access attached PHY devices. When this bit is 0, the MDIO interface is disabled and the MDIO signals remain inactive. A write to this bit only takes effect if the Clock Divide is set to a non-zero value.
5:0	0x0	R/W	Clock Divide[5:0]: See Accessing PHY Configuration Registers, through MDIO Using the Management Interface.

Table 3. MDIO Control Word (0x504)
Bits	Default Value	Type	Description
31:29	N/A	RO	Reserved
28:24	0x0	R/W	TX_PHYAD: This controls the PHY address being accessed.
23:21	N/A	RO	Reserved
20:16	0x0	R/W	TX_REGAD: This controls the register address being accessed.
15:14	0x0	R/W	TX_OP: This field controls the type of access performed when a 1 is written to initiate. 01-Write Access 10-Read Access
13:12	N/A	RO	Reserved
11	0x0	WO	Initiate: Writing a 1 to this bit starts an MDIO transfer.
10:8	N/A	RO	Reserved
7	0x0	RO	MDIO ready: When set, the MDIO is enabled and ready for a new transfer. This is also used to identify when a previous transaction has completed (for example, Read data is valid).
6:0	N/A	RO	Reserved

Table 4. MDIO Write Data (0x508)
Bits	Default Value	Type	Description
31:16	N/A	RO	Reserved
15:0	0x0000	R/W	Write Data

Table 5. MDIO Read Data (0x50C)
Bits	Default Value	Type	Description
31:17	N/A	RO	Reserved
16	0x0	RO	MDIO Ready: This is a copy of Bit[7] of the MDIO Control Word.
15:0	0x0000	RO	Read Data: Only valid when MDIO ready is sampled High.