Figure 1 illustrates clock resource sharing across
multiple instantiations of the core when using RGMII at 1 Gbps in 7 series devices using HP I/O. Figure 2 illustrates clock resource sharing across
multiple instantiations of the core when using RGMII at 1 Gbps in 7 series devices using HR I/O. For all instantiations,
gtx_clk and gtx_clk90, where present, can be shared
between multiple cores, resulting in a common clock domain across the device. The receiver
clocks cannot be shared. Each core is provided with its own local version of rgmii_rxc from the connected external PHY device as shown in the
following figures.
In both figures, the upper core instance has been generated with the Shared Logic option enabled including an IDELAYCTRL as illustrated. The other core instances have been generated without the Shared Logic option enabled.
The following figures illustrate three
cores. However, more can be added using the same principle. This is done by instantiating
further cores without the Shared Logic option and sharing gtx_clk across all instantiations. The receiver clock, which cannot be shared, is
unique for every instance of the core.