rx_client_fifo_2g5 - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The rx_client_fifo_2g5 is built around a Dual Port instantiated block RAM, giving a total memory capacity of 4,096 bytes. The receive FIFO writes in data received through the TEMAC core. If the frame is not errored, that frame is presented on the AXI4-Stream FIFO interface for reading by you, (in this case the basic_pat_gen module). If the frame is errored, that frame is dropped by the receive FIFO.

If the receive FIFO memory overflows, the frame currently being received is dropped, regardless of whether it is a good or bad frame, and the signal rx_overflow is asserted.

Situations in which the memory can overflow are:

  • The FIFO can overflow if the receiver clock is running at a faster rate than the transmitter clock or if the inter-packet gap between the received frames is smaller than the interpacket gap between the transmitted frames. If this is the case, the TX FIFO is not able to read data from the RX FIFO as fast as it is being received.
  • The FIFO size of 4,096 bytes limits the size of the frames that it can store without error. If a frame is larger than 4,000 bytes, the FIFO can overflow and data is then lost. It is therefore recommended that the example design is not used with the TEMAC solution in jumbo frame mode for frames larger than 4,000 bytes.