Due to the number of clock domains in this core, the reset structure is not simple and involves many separate reset regions, with the number of regions being dependent upon the particular parameterization of the core.
The following figure shows the most
common reset structure for the core. Because the rx_reset and
tx_reset outputs have dependencies on the glbl_rstn and tx/rx_axi_rstn
inputs they cannot be used in their creation.
Figure 1. Reset Architecture
