The following figure illustrates clock
resource sharing across multiple instantiations of the core when using RGMII at 1 Gbps. For
all instantiations, gtx_clk can be shared between multiple
cores, resulting in a common clock domain across the device. The receiver clocks cannot be
shared. Each core is provided with its own local version of rgmii_rxc from the connected external PHY device as shown in the following figure
.
In this figure, the upper core instance has been generated with the Shared Logic option enabled. In both cases this includes an IDELAYCTRL as illustrated. The other core instances have been generated without the Shared Logic option enabled.
The following figure illustrates three
cores. However, more can be added using the same principle. This is done by instantiating
further cores and sharing gtx_clk across all instantiations.
The receiver clock, which cannot be shared, is unique for every instance of the core.
