The following table describes the Phase
Adjustment Register that has units of nanoseconds. This value is added to the synchronized
value of the RTC nanoseconds field, and the RTC timing signals are then derived from the
result. This phase offset is therefore applied to the clk8k
signal. As an example, writing the value of the decimal 62500 (half of an 8 kHz clock
period) to this register would invert the clk8k
signal with
respect to a value of 0. Therefore, this register can provide fine grained phase alignment
of these signals to a 1 ns resolution.
Bits | Default Value | Type | Description |
---|---|---|---|
31:30 | 0 | RO | Reserved |
29:0 | 0 | R/W | ns value relating to the phase offset for all RTC derived timing signals (clk8k). |