ID Register (0x4F8) - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
Document ID
PG051
Release Date
2023-11-07
Version
9.0 English
Table 1. ID Register (0x4F8)
Bits Default Value Type Description
31:24 z 1 RO Major Rev
23:16 y 1 RO Minor Rev
15:8 N/A RO Reserved
7:0 x 1 RO Patch Level (0-No patch, 1-Rev1)
  1. The default values depend upon the version of the core being used.
Table 2. Ability Register (0x4FC)
Bits Default Value Type Description
31:17 N/A RO Reserved
16 0 RO PFC Support . This bit indicates that the core has been generated with PFC support.
15:11 N/A RO Reserved
10 1 1 RO Frame filter available
9 1 1 RO Half duplex capable
8 1 1 RO Statistics Counters available
7:4 N/A RO Reserved
3 1 1 RO 2.5G Ability: If set, the core is 2.5G capable
2 1 1 RO 1G Ability: If set, the core is 1G capable
1 1 1 RO 100M Ability: If set, the core is 100M capable
0 1 1 RO 10M Ability: If set, the core is 10M capable
  1. Depends on core abilities selected.