Figure 1 shows the timing of a
normal inbound frame transfer at 1 Gbps. Figure 2 shows the timing at
10/100 Mbps when the core is configured for MII/GMII or RGMII. For the Internal option the
timing for 100 Mbps is shown in Figure 3. For 10 Mbps the rx_axis_mac_tvalid is only
enabled once every 100 cycles. You must be prepared to accept data at any time; there is no
buffering within the MAC to allow for latency in the receive logic. When the frame reception
begins, the data is transferred on consecutive validated cycles to the receive logic until
the frame is complete. The MAC asserts the rx_axis_mac_tlast
signal to indicate that the frame has completed with rx_axis_mac_tuser signal being used to indicate any errors.
Frame parameters (destination address, source address, length/type, and optionally FCS) are supplied on the data bus according to the timing diagram. The abbreviations are described in Table 1.
If the length/type field in the frame has the length interpretation and this indicates that the inbound frame has been padded to meet the Ethernet minimum frame size specification, this padding is not passed to you in the data payload. However, this is excepted when the FCS passing is enabled. See User-Supplied FCS Passing.
When user-supplied FCS passing is disabled,
rx_axis_mac_tvalid = 0 between frames for the duration of
the padding field (if present), the FCS field, carrier extension (if present), the
interframe gap following the frame, and the preamble field of the next frame. When
user-supplied FCS passing is enabled, rx_axis_mac_tvalid = 0
between frames for the duration of carrier extension (if present), the interframe gap, and
the preamble field of the following frame.