Clock Sharing across Multiple Cores with GMII for Tri-Speed Operation - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

Because both mii_tx_clk and gmii_rx_clk are sourced by the external PHY device connected to the GMII/MII, it is not possible to share global transmitter or receiver clock resources across multiple instantiations of the core. Each instance of the core requires its own endpoint clocking resources. RGMII provides a more optimal solution because it does allow transmitter clock resources to be shared. See RGMII for more information.

The following figure illustrates that the upper core instance has been generated with the Shared Logic option enabled. For the GMII, this instantiates an IDELAYCTRL as illustrated. The other core instances have been generated without the Shared Logic option enabled. The following figure illustrates three cores. However, more can be added using the same principle. This is done by instantiating further cores without the Shared Logic option.

Figure 1. Clock Resource Sharing for Tri-Speed GMII

If the GTX clock (gtx_clk ) is sourced from a BUFG, it should be connected to multiple instances of the TEMAC IP, using multiple BUFGs, as shown in the following figure. This is required to limit the number of BUFGs that are cascaded together up to 9.

Figure 2. Clock Resource Sharing for Tri-Speed GMII with GTX Clock BUFG