MDIO Configuration and Control - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
PG051
Release Date
2024-12-11
Version
9.0 English

Access to the MDIO interface through the management interface is entirely register mapped. To perform an MDIO write, the write data must first be written to the MDIO Write Data register, shown in Table 4. The MDIO write transaction is then initiated by a write to the MDIO Control Word register, shown in Table 3, with Initiate (Bit[11]) set to 0x1, OP (Bits[15:14]) set to 0x1, and the PHYAD and REGAD set according to the PHY and Register being accessed. This triggers the MDIO Ready bit to de-assert and it remains de-asserted until the MDIO transaction is completed.

To perform an MDIO read, the read transaction is initiated by a write to the MDIO Control Word register, shown in Table 3, with Initiate (Bit[11]) set to 0x1, OP (Bits[15:14]) set to 0x2, and the PHYAD and REGAD set according to the PHY and Register being accessed. This triggers the MDIO Ready bit to de-assert and it remains de-asserted until the MDIO transaction is completed. When the MDIO Ready is re-asserted the read data is ready to be read from the MDIO Read data register, shown in Table 5.

  • It is possible to either poll the MDIO Control register or the MDIO Read Data register to check the status of MDIO Ready. Alternatively, the MAC interrupt can be used (see Interrupt Controller).