Receiver Logic - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

In this implementation, the input clock is used for sampling the RGMII RX signal at the device IOBs. This creates placement constraints: a clock capable input pin must be selected, and all other input RGMII RX signals must be placed in the respective byte group. See the UltraScale Architecture Clocking Resources User Guide (UG572) for more information.

The following figure shows that the input clock is passed through two parallel global clock routes using BUFG components. One global clock route is used to clock the receiver IOB logic and the other global clock route is for clocking user-side logic which connects to the receiver AXI4-Stream interface of the core. The reason for providing two parallel clock paths is to help Vivado to close timing on the input paths.

It has been observed that, for some devices, Vivado might not succeed in closing timing on the input paths if the input clock net is heavily loaded. Splitting the single clock route into two parallel routes reduces the load on the clock nets and thus helps in closing timing. However, you can modify the clocking structure to use only one global clock path if you can meet the input timing for your selected devices. To perform this, edit the core instance unencrypted HDL file, <component_name_rgmii_v2_0_if> present in the core instance synth/implementation directory.

The IODELAY elements can be adjusted to fine-tune the setup and hold times at the RGMII IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the XDC which can be edited if desired. See Constraining the Core.

Closely linked to the clock logic is the use of the rx_enable clock enable derivation. This must be provided to the Ethernet MAC core level. All user logic uses the AXI4-Stream interface handshaking to throttle the data to allow for the differing data widths between the 4-bit MII and the core 8-bit user datapath.

Figure 1. Tri-Speed RGMII Receiver and Clock Logic

The previous figure shows that IODELAY elements are used by the receiver logic. An IDELAYCTRL module must be instantiated in the design. For the RGMII, this is included in the <component_name>_support level, present in the core if the Shared Logic option is selected.