Core-Initiated Request - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
Release Date
9.0 English

There are three methods of generating a PFC frame, all of which assume that TX PFC is enabled and any actively used priority has the relevant TX priority enable set to 1.

  1. The client asserts one or more of the eight tx_pfc_p[0-7]_tvalid signals. If the tx_pfc_p[0-7]_tvalid signal is asserted for more than a single cycle then this is considered to be an XOFF request and the MAC refreshes the relevant quanta at the link partner whenever a new PFC frame is transmitted until the tx_pfc_p[0-7]_tvalid is de-asserted. If tx_pfc_p[0-7]_tvalid is asserted for a single cycle, it is assumed that any required refresh is directly controlled by a subsequent reassertion of the respective tvalid as required.
  2. The client keeps a priorities tx_pfc_p[0-7]_tvalid signal High and the internal quanta count of the Ethernet MAC reaches the pre-programmed refresh value for that priority. On reaching this refresh value, the MAC “refreshes” the priority pause request by resending a new PFC frame with the pre-programmed pause value for the given priority. For each of the eight priorities, there is a configuration register that contains both the pause duration and the refresh value. (see Table 9)
  3. The client has held a tx_pfc_p[0-7]_tvalid High for more than one cycle this is then de-asserted and the TX auto XON feature is enabled. This results in a new PFC frame with the relevant priorities quanta being both enabled and forced to zero. This is considered to be an XON request for that priority.

When any new PFC frame is transmitted it also resends the quanta for any currently active, enabled priority, effectively refreshing each priority quanta at the link partner. This also restarts the internal quanta count.

The eight tx_pfc_p[0-7]_tvalid signals are synchronous with respect to tx_clk0 . The various transmit methods can be seen in the following figure. In the following figure, the tx_pfc_p0_tvalid is asserted and held High. This results in a PFC frame with only the P0 quanta enabled (set to 0xFFFF). Several cycles later, tx_pfc_p2_tvalid is asserted for a single cycle and this results in a new PFC frame with both the P0 and P2 quantas enabled (and restarts the internal quanta count).

The internal quanta count subsequently reaches the programmed refresh value for Priority 0 and a refresh PFC frame is sent with only the P0 quanta enabled (as all other tvalid requests are Low). tx_pfc_p6_tvalid is asserted and held High and this also results in a new PFC frame (P6 XOFF) with both P0 and P6 quantas enabled. Finally, tx_pfc_p0_tvalid is de-asserted resulting in another PFC frame (P0 XON). This has both the P0 and P6 quantas enabled with the P0 quanta set to 0x0.

Figure 1. TX PFC Frame Transmission