The following table describes the reset signals, the clock signals that are input to the core, and the outputs that can be used to select between the three operating speeds. The clock signals are generated in the top-level wrapper provided with the core.
| Signal | Direction | Description |
|---|---|---|
| glbl_rstn | In | Active-Low asynchronous reset for entire core. |
| rx_axi_rstn | In | Active-Low RX domain reset |
| tx_axi_rstn | In | Active-Low TX domain reset |
| rx_reset | Out | Active-High RX software reset from Ethernet MAC core level |
| tx_reset | Out | Active-High TX software reset from Ethernet MAC core level |
| gtx_clk | In | Global 125 MHz clock. For 2.5 Gbps Ethernet speed is 312.5 MHz. |
| refclk | In |
Required for idelayctrl, 200–300 MHz. For UltraScale architecture devices the range is 300–1333 MHz. |
| rx_usr_clk2 | In | Only available when the Physical Interface is set to Internal and Internal Mode Clock Source set to RX User Clk2. 125 MHz Clock for the MAC RX datapath. |
| tx_mac_aclk | Out |
Clock for the transmission of data on the physical interface. 312.5 MHz at 2.5 Gbps, 125 MHz at 1 Gbps, 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps. This clock should be used to clock the physical interface transmit circuitry and the TX AXI4-Stream transmit circuitry. See the appropriate section: Physical Interface for 7 Series and Zynq 7000 Devices |
| rx_mac_aclk | Out |
Clock for the reception of data on the physical interface. 312.5 MHz at 2.5 Gbps, 125 MHz at 1 Gbps, 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps. This clock should be used to clock the physical interface receive circuitry and the RX AXI4-Stream receive circuitry. See the appropriate section: Physical Interface for 7 Series and Zynq 7000 Devices |
| clk_enable | In |
Only available when the core is generated in Internal with tri-speed operation. This signal is input from the Ethernet 1G/2.5G PCS/PMA or SGMII core and used by the TEMAC as clock enable signal. For 1000 Mbps speeds, this signal is always asserted and for 10/100 Mbps speeds this signal pulsates once every 100/10 clock cycles. For more details, see 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047). |
| clk_enable_rx | In |
Only available when the Physical Interface is set to Internal and Internal Mode Clock Source set to RX User Clk2. This signal is input from the Ethernet 1G/2.5G PCS/PMA or SGMII core and used by the TEMAC as clock enable signal for the RX datapath. For 1,000 Mbps speeds, this signal is always asserted and for 10/100 Mbps speeds, this signal pulsates once every 100/10 clock cycles. For more details, see 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047). |
| speedis100 | Out | This output is asserted when the core is operating at 100 Mbps. It is derived from either Bits[13:12] of the MAC Speed Configuration register. If the optional Management Interface is not present, this is derived from configuration vector Bits[13:12]. |
| speedis10100 | Out | This output is asserted when the core is operating at either 10 Mbps or 100 Mbps. It is derived from either Bits[13:12] of the MAC Speed Configuration register. If the Management Interface is not present, this is derived from configuration vector Bits[13:12]. |
| gtx_clk_out | Out |
Only available when using RGMII in AMD Artix™ 7 or AMD Kintex™ 7 devices, and only then when the Shared Logic option (see Shared Logic) is selected with the “Include shared logic in core” option. This output clock can be used by other TEMAC core instances when sharing clocking resources. ForAMD Virtex™ 7, MMCM is not a sharable resource and thus gtx_clk_out, and gtx_clk90_out are not listed. See the Physical Interface for 7 Series and Zynq 7000 Devices for details. See Figure 1 orFigure 2 for a connection illustration. This clock has a 0o phase shift with respect to the gtx_clk input and is used for RGMII data transmission. |
| gtx_clk90_out | Out |
Only available when using RGMII in Artix 7 or Kintex 7 devices, and when the Shared Logic option (see Shared Logic) is selected with the “Include shared logic in core” option. This output clock can be used by other TEMAC core instances when sharing clocking resources. See See Figure 1 orFigure 2 for a connection illustration. This clock has a 90o phase shift with respect to the gtx_clk input and is used for the RGMII transmitter clock forwarding. |