The basic pattern generator for 10, 100, 1000 Mbps data rates are described in the following files:
<component_name>_basic_pat_gen.v[hd]
<component_name>_axi_pat_gen.v[hd]
<component_name>_axi_pat_check.v[hd]
<component_name>_axi_mux.v[hd]
<component_name>_axi_pipe.v[hd]
<component_name>_address_swap.v[hd]The basic pattern generator has two main functional modes: loopback and generator. In loopback, the data from the RX FIFO is passed to the address swap module and passed from there to the TX FIFO. In generator mode, the TX data is provided by the pattern generator, with RX Data being optionally checked by the pattern checker.