TX PTP Packet Buffer - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The TX PTP packet buffer is illustrated in the following figure. This packet buffer provides working memory to hold the PTP frames which are required for transmission. The software drivers, through the AXI4-Lite configuration bus, can read/modify/write the PTP frame contents, and request transmission of the appropriate PTP frames, when required.

The PTP packet buffer is implemented in dual-port block RAM. Port A of the block RAM is connected to the configuration bus and all addresses in the buffer are read/writable. Port B of the block RAM is connected to the TX Arbiter module, allowing PTP frames to be read out of the block RAM and transmitted.

The TX PTP Packet Buffer is divided into eight identical buffer sections as illustrated. Each section contains 256 bytes, which are formatted as follows:

  • The first byte, at address zero, contains a frame length field. This indicates how many bytes make up the PTP frame that is to be transmitted from a particular PTP buffer.
  • The next seven bytes from addresses 1 to 7 are reserved for future use.
  • The PTP frame data itself is stored from address 8 onwards. The amount of addresses used is dependent on the indicated frame length field, which is different for each PTP frame type. Each PTP buffer provides a maximum of 244 bytes (more than that required for the largest PTP frame). Each PTP frame holds the entire MAC frame (with the exception of any required MAC padding or CRC—these are automatically inserted by the transmit logic) from the Destination Address field onwards.
  • The top four addresses of each buffer, from address 0xFC to 0xFF are reserved for a timestamp field. At the beginning of PTP frame transmission from any of the eight buffers, the Timestamping Logic samples the Real-Time Clock. Following the end of the PTP frame transmission, this captured timestamp is automatically written into this location to accompany the frame for which it was taken.

Despite the logic and formatting of each individual PTP buffer being identical, the block RAM is pre-initialized at device configuration to hold template copies of each of the PTP frames, as indicated in the following figure. This shows that the first seven memory segments are in use. PTP Buffer number 8 is currently unused and could therefore be used by proprietary applications.

The TX PTP Packet Buffer Control Register is defined for the purpose of requesting which of the eight TX PTP Buffers are to be transmitted. It is possible to request more than a single frame at one time (indeed it is possible to request all 8). When more than one frame is requested, the TX PTP Buffer logic gives a priority order to the lowest PTP Buffer Number that has been requested.

The TX PTP Packet Buffer Control Register also contains a frame waiting field. This can be read by the software drivers to determine which of the previously requested PTP frames have been sent, and which are still queued.

Following transmission completion of each requested PTP frame, a dedicated interrupt signal, interrupt_ptp_tx, is generated by the core. On the assertion of the interrupt, the captured timestamp is already available in the upper four bytes of the buffer, and the tx_packet field of the TX PTP Packet Buffer Control Register indicates the most recently transmitted Buffer Number.

The software drivers available from AMD, using the AXI4-Lite and dedicated interrupts, use this interface too, as defined by the IEEE802.1AS protocol, periodically update specific fields within the PTP packets, and request transmission of these packets.

Figure 1. TX PTP Packet Buffer Structure