These techniques can help close timing on I/O paths covered
by set_input_delay /set_output_delay constraints:
- TX Path
- Lock the clocking elements used to generate the transmit clock, that is the MMCM and BUFG, to be in the same clock region. Locking the TX I/O pins to this clock region results in better timing margins.
- RX Path
- Lock the BUFG on the RX clock input and the RX I/O pins to be in the same clock region.
To illustrate how these techniques can be used, the following constraints are developed for the TEMAC example design generated for an XCKU040-FFVA1156 device in RGMII:
# 200 MHz input clock
set_property PACKAGE_PIN AF10 [get_ports clk_in_p]
set_property PACKAGE_PIN AG10 [get_ports clk_in_n]
# RGMII TX pins
set_property PACKAGE_PIN AH9 [get_ports rgmii_txc]
set_property PACKAGE_PIN AH8 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN AK8 [get_ports rgmii_txd[0]]
set_property PACKAGE_PIN AL8 [get_ports rgmii_txd[1]]
set_property PACKAGE_PIN AJ9 [get_ports rgmii_txd[2]]
set_property PACKAGE_PIN AJ8 [get_ports rgmii_txd[3]]
# RGMII RX pins
set_property PACKAGE_PIN AG11 [get_ports rgmii_rxc]
set_property PACKAGE_PIN AM11 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN AE13 [get_ports rgmii_rxd[0]]
set_property PACKAGE_PIN AF13 [get_ports rgmii_rxd[1]]
set_property PACKAGE_PIN AK13 [get_ports rgmii_rxd[2]]
set_property PACKAGE_PIN AL13 [get_ports rgmii_rxd[3]]
# BUFG on 200 MHz input clock
set_property CLOCK_REGION X2Y0 [get_cells {example_clocks/bufg_clkin1}]
# BUFG on GTX Clock
set_property CLOCK_REGION X2Y0 [get_cells {example_clocks/clock_generator/
clkout1_buf}]
# BUFG on RX Clock input
set_property CLOCK_REGION X2Y0 [get_cells -hier -filter {NAME =~ */
rgmii_interface/bufg_rgmii_rx_clk}]
set_property CLOCK_REGION X2Y0 [get_cells -hier -filter {NAME =~ */
rgmii_interface/bufg_rgmii_rx_clk_iddr}]
# Create Pblock to place the design in the vicinity of IO pins
startgroup
create_pblock pblock_1
resize_pblock pblock_1 -add CLOCKREGION_X2Y0:CLOCKREGION_X2Y0
endgroup
add_cells_to_pblock pblock_1 -top