IP Facts - IP Facts - 9.0 English - PG051

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
Document ID
PG051
Release Date
2024-12-11
Version
9.0 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD Versal™ Adaptive SoC, AMD UltraScale+™ families, AMD UltraScale™ families, AMD Zynq™ 7000 SoC, 7 series FPGAs
Supported User Interfaces AXI4-Lite, AXI4-Stream
Resources Performance and Resource Use web page
Provided with Core
Design Files Encrypted RTL
Example Design VHDL and Verilog
Test Bench Demonstration Test Bench
Constraints File XDC
Simulation Model Verilog and VHDL
Supported S/W Driver 2 N/A
Tested Design Flows 2
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 54251
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.
  2. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).