|
Core Specifics |
| Supported Device Family
1
|
AMD UltraScale+™
families, AMD UltraScale™
families, AMD Zynq™ 7000 SoC, 7 series
FPGAs |
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream |
| Resources |
Performance and Resource Use web page
|
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
VHDL and Verilog |
| Test Bench |
Demonstration Test Bench |
| Constraints File |
XDC |
| Simulation Model |
Verilog and VHDL |
| Supported S/W Driver
2
|
N/A |
| Tested Design
Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 54251
|
| All Vivado IP Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|