Accessing PHY Configuration Registers, through MDIO Using the Management Interface - 9.0 English

The Management Interface is also used to access the MDIO interface of the core. The MDIO interface supplies a clock to the connected PHY, mdc. This clock is derived from the s_axi_aclk signal using the value in the Clock Divide[5:0] configuration register. The frequency of mdc is given:

The frequency of mdc given by the previous equation should not exceed 2.5 MHz to comply with the IEEE 802.3-2008 specification for this interface. To prevent mdc from being out of specification, the Clock Divide[5:0] value powers up at 00000, and while this value is in the register, it is impossible to enable the MDIO interface.

For details of the register map of PHY layer devices and a fuller description of the operation of the MDIO interface itself, see IEEE 802.3-2008.