The following figure illustrates clock
resource sharing across multiple instantiations of the core. For all instantiations, gtx_clk , where present, can be shared between multiple cores,
resulting in a common clock domain across the device. The receiver clocks cannot be shared.
Each core is provided with its own local version of rgmii_rxc
from the connected external PHY device as shown.
In this figure, the upper core instance has been generated with the Shared Logic option enabled. In both cases, this includes an IDELAYCTRL as illustrated. The other core instances have been generated without the Shared Logic option enabled.
The following figure shows three cores. However, more can be added using the same principle.
