Issues with the MDIO - 9.0 English

See Accessing PHY Configuration Registers, through MDIO Using the Management Interface for detailed information about performing MDIO transactions.

Things to check for:

• Check that the MDC clock is running and that the frequency is 2.5 MHz or less. If using the MDIO control registers to perform MDIO accesses, the MDIO interface does not work until the clock frequency is set with CLOCK_DIVIDE. The MDIO clock with a maximum frequency of 2.5 MHz is derived from the s_axi_aclk clock.
• Ensure that the TEMAC and PHY are not held in reset. Be sure to check the polarity of the reset to your external PHY. Many PHYs have an active-Low reset.
• Read from a configuration register that does not have all 0s as a default. If all 0s are read back, the read was unsuccessful.
• If using the management interface to access the MDIO, check if the issue is with the MDIO control registers or if there are also issues reading and writing MAC registers with the management interface.
• If accessing MDIO registers of the Ethernet 1G/2.5G PCS/PMA or SGMII core, check that the PHYAD field placed into the MDIO frame matches the value placed on the phyad[4:0] port of the Ethernet 1G/2.5G PCS/PMA or SGMII core.
• Has a simulation been run? Verify in simulation and/or a Vivado analyzer tool capture that the waveform is correct for accessing the management interface for an MDIO read/write. The demonstration test bench delivered with the core provides an example of MDIO accesses.