The logic required to implement the MII transmitter logic
is illustrated in Figure 1 .
mii_tx_clk is provided by the external PHY device connected to the MII. As shown,
this is placed onto a global clock routing (BUFG) to provide the clock for all transmitter
logic, both within the core and for the user-side logic which connects to the TX AXI4-Stream interface of the core.
To match the user data rate (which uses an 8-bit datapath)
and the MII (which uses a 4-bit datapath), the TX AXI4-Stream interface is
throttled, using tx_axis_mac_tready, under control of the MAC to limit data transfers
to every other cycle. Figure 1 also
illustrates how to use the physical transmitter interface of the core to create an external
MII. The signal names and logic shown in this figure exactly match those delivered with the
core. Figure 1 shows that the output
transmitter signals are registered in device IOBs before driving them to the device pads.