RGMII for 7 Series Devices - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
Document ID
PG051
Release Date
2023-11-07
Version
9.0 English
Figure 1. RGMII Logic for 7 Series Using HR I/O Devices

The previous figure shows that the IDELAYCTRL module is instantiated at the <component_name>_support level. If the Shared Logic level option is not selected, ensure that an IDELAYCTRL is instantiated elsewhere in the user design.

In the previous figure two output ports gtx_clk_out and gtx_clk90_out are present. These can be directly connected to gtx_clk and gtx_clk90 clock inputs for secondary core instances, if they are generated with the “Shared logic included in example design” option selected in the Vivado IDE.

Figure 2. RGMII Logic for 7 Series Using HP I/O Devices

The previous figure shows that the IDELAYCTRL module is instantiated at the <component_name>_support level. If the Shared Logic level is not selected, ensure that an IDELAYCTRL is instantiated elsewhere in the user design.