Increment of Nanoseconds Field - 9.0 English

The following figure shows the implementation used to create the RTC nanoseconds field. This is performed by the use of an implementation-specific 20-bit sub-nanoseconds field. The nanoseconds and sub-nanoseconds fields can be considered to be concatenated together. All RTC logic within the core is synchronous to the RTC Reference clock, gtx_clk.

There are two stages to the implementation:

1. Controlled Frequency RTC

The RTC Increment Value illustrated in the previous figure is set directly from the RTC Increment Value Control Register. The upper six bits of this register align with the lower six bits of the RTC nanoseconds field. The lower 20 bits of the RTC Increment Value align with the 20-bit sub-nanoseconds field. It is assumed that the frequency of the RTC reference clock is known by the processor to program the increment value correctly. For example, if the RTC is being clocked from a 125 MHz clock source, a nominal increment value of 8 ns should be programmed (by writing the value 0x800000 into the RTC Increment Value Control Register). However, if the microprocessor determines that this clock is drifting with respect to the grand master clock, it can revise this nominal 8 ns up or down by a very fine degree of accuracy.

The “step 1” addition illustrated in the previous image (of current counter value plus increment) occurs on every clock cycle of the RTC reference clock. The result from this addition forms the new value of the “controlled frequency RTC” nanoseconds field. This controlled frequency RTC initializes to zero, following a reset, and continues to increment smoothly on every RTC reference clock cycle by the current value contained in the RTC Increment Value Control Register.

The previous image illustrates that 26 bits have been reserved for the Increment Value, the upper 6 bits of which overlap into the nanoseconds field. For this reason, the largest per-cycle increment = 1 ns × 26 = 64 ns. The lowest clock period which is expected to increment this counter is 40 ns (corresponding to the 25 MHz MAC clock used at 100 Mbps speeds). So, this should satisfy all allowable clock periods.

1. Synchronized RTC

The value contained in the RTC Seconds Field Offset Control and RTC Nanoseconds Field Offset Control written by the microprocessor, is then applied to the free running “controlled frequency RTC” counter. This is used by the microprocessor to:

• Initialize the power-up value of the Synchronized RTC.
• Apply step corrections to the Synchronized RTC (when a slave), based on the timing of PTP packets received from the Grand Master Clock RTC.

The “step 2” addition illustrated in the previous image (of controlled frequency RTC value plus offset) occurs on every clock cycle of the RTC reference clock. The result from this addition forms the new value of the Synchronized RTC nanoseconds field. It is this version of the RTC nanoseconds field which is made available as an output of the core – the rtc_nanosec_field[31:0] port.