TX PTP Packet Buffer Address Space - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The TX PTP Packet buffers are only available when the AVB functionality is included in the TEMAC core.

The Address space of the TX PTP Packet Buffer is 2K in total, representing the size of a single FPGA block 18K RAM. Every byte of this block RAM is accessible by the CPU. This address space is divided equally into eight separate buffers of 256 bytes, each of which is capable of storing a unique PTP frame. Seven of these buffer locations are pre-initialized with standard PTP frame syntax. However, each byte can be modified if desired.

Within each single buffer, the initial byte is used as a length field used to indicate to the core logic the number of bytes to be transmitted for that frame. An entire PTP frame (from MAC Destination Address through to the last byte from the data field) is then stored, starting at the eighth address of that particular buffer. Following PTP frame transmission from one of these buffers, the TX Timestamp captured for that frame is written into the top four bytes of the buffer used. See TX PTP Packet Buffer for more details. A list of the TX PTP Buffers is shown in the following table.

Table 1. TX PTP Buffers
Address (Hex) Description
0x11000-0x110FC TX PTP Buffer 0 – Initialized for a SYNC frame.
0x11100-0x111FC TX PTP Buffer 1 – Initialized for a Follow up frame.
0x11200-0x112FC TX PTP Buffer 2 – Initialized for a Pdelay request frame.
0x11300-0x113FC TX PTP Buffer 3 – Initialized for a Pdelay response frame.
0x11400-0x114FC TX PTP Buffer 4 – Initialized for a Pdelay response follow up frame.
0x11500-0x115FC TX PTP Buffer 5 – Initialized for an Announce frame.
0x11600-0x116FC TX PTP Buffer 6 – Initialized for a Signaling frame.
0x11700-0x117FC TX PTP Buffer 7