RX PTP Packet Buffer Control Register - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
Document ID
PG051
Release Date
2024-12-11
Version
9.0 English

The following table defines the associated control register of the RX PTP Packet Buffers used by the software to monitor the position of the most recently received PTP frame.

Table 1. RX PTP Packet Buffer Control Register (0x12004)
Bits Default Value Type Description
31:12 0 RO Reserved
11:8 0 RO rx_packet. Indicates the number (block RAM bin position) of the most recently received PTP packet.
7:1 0 RO Reserved
0 0 WO

rx_clear. When written with a one, forces the buffer to empty, in practice moving the write address to the same value as the read address.

If read, always returns 0.
  1. A read or a write to this register clears the interrupt_ptp_rx interrupt (asserted after each successful PTP packet reception).