Revision History - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)
Document ID
PG051
Release Date
2023-11-07
Version
9.0 English

The following table shows the revision history for this document.

Section Revision Summary
11/07/2023 Version 9.0
General Updates Entire document
05/17/2023 Version 9.0
Clock, Speed Indication, and Reset Signal Definition Added a note for Table.
12/02/2022 Version 9.0
Flow Control Interface (IEEE 802.3) Added a table note
05/09/2022 Version 9.0
I/O Delay Calibration Ports for TEMAC RGMII Interface Added a new table.
08/05/2021 Version 9.0
User Error Indication Added tuser assertion information and updated for Vivado 2021.1 release.
07/08/2020 Version 9.0
Table 1 Updated rx/tx_configuration_vector
User Error Indication Added paragraph at the end
Frame Collisions – Half-Duplex Operation Only Added paragraph at the end
RGMII and RGMII Added UltraScale+ caution note
04/04/2018 Version 9.0
Product Specification
  • Updated mac_irq description in Interrupt Signals table
  • Updated rtc_nanosec_field and rtc_sec_field descriptions in AVB Specific Signals table
  • Added header file description in Register Space section
  • Added bit description to Interrupt Controller section
Designing with the Core Added MAC description in User Error Indication section
10/04/2017 Version 9.0
Designing with the Core
  • Updated rx_pfc_p[0-7]_tready description in Pause Frame Reception Enabled section
  • Updated description in Finding the Ideal Phase Shift Value section.
  • Updated code in Timing Violations on I/O Paths in GMII/RGMII – UltraScale Architecture Devices section.
10/05/2016 Version 9.0
IP Facts Added Spartan-7
XON/XOFF Extended Functionality Added note
RGMII Added a Caution note
User Parameters Updated Vivado IDE Parameter to User Parameter Relationship table.
Upgrading Added description in IP Upgrade.
04/06/2016 Version 9.0
Product Specification
  • Updated Important description in MAC description.
  • Updated Table 2-13: Clock and Speed Indication Signals.
  • Updated Bits[79:32] in Table 2-21: tx_configuration_vector Bit Definitions.
  • Updated Bits[79:32] in Table 2-22: rx_configuration_vector Bit Definitions.
  • Updated RX Alignment Errors and RX Bad Opcode descriptions in Table 2-24: Statistics Counter Definitions.
Design Flow Steps
  • Added description in Maximum Permitted Frame Length section.
  • Updated Fig. 4-2.
  • Added Internal mode Clock Source in Design Flow Steps chapter.
  • Added Int_Clk_Src in Table 4-1: Vivado IDE Parameter to User Parameter Relationship.
  • Added rx_usr_clk2 in Table 4-3: TEMAC Solution Frequency Requirements.
11/18/2015 Version 9.0
UltraScale Devices Added support for UltraScale+ families.
09/30/2015 Version 9.0
Designing with the Core
  • Updated the Resource Utilization section.
  • Updated speedis100 description in Clock and Speed Indication Signals.
  • Updated Fig. 3-56: Management Register Write Timing.
  • Updated RX Oversize Frames description in Statistics Counter Definitions.
  • Added loopback logic availability in Example Design section.
  • Updated Basic Pattern Generator Module for 10, 100, 1000 Mbps Data Rates.
  • Added Basic Pattern Generator Module for 2.5 Gbps Data Rate section.
  • Added description in 10, 100, 1000 Mbps Ethernet FIFO section.
  • Added 2.5 Gbps Ethernet FIFO section.
  • Added 2.5 Gbps description in Test Bench Functionality section.
04/01/2015 Version 9.0
Product Specification
  • Added 2.5 Gbps Ethernet feature throughout product guide.
  • Updated description in Ethernet Overview.
  • Updated Table 2-22: Clock and Speed Indication Signals.
  • Updated Table 2-45: Ability Register (0x4FC).
  • Added GMII/RGMII for UltraScale Devices and MII or Internal Interface for UltraScale Devices sections.
  • Updated description in Clocking section.
Designing with the Core
  • Updated description in 10 or 100 Mbps Ethernet MAC Core Interfaces MII Transmitter and Receiver Interface sections.
  • Updated description in 1 Gbps Ethernet MAC Core Interfaces GMII Receive Interface section.
  • Updated description in RGMII section.
  • Updated description in Tri-Speed Ethernet MAC Core Interfaces (UltraScale) section.
  • Updated Caution note in Ethernet 1000BASE-X PCS/PMA or SGMII Core section.
Design Flow Steps
  • Added Data Rate section and updated Figs. 4-1 to 4-5
  • Updated Table 4-1: Vivado IDE Parameter to User Parameter Relationship.
  • Added Virtex UltraScale in Table 4-2: Supported Speed Grades.
  • Added UNISIM important note in Simulation section.
  • Updated Synthesis and Implementation section.
Upgrading Updated the appendix.
Debugging Added Timing Violations on I/O Paths in GMII/RGMII – UltraScale Architecture Devices section
10/01/2014 Version 8.3
MDIO Interface Added MDIO interface and I/O buffer selection
04/02/2014 Version 8.2
Product Specification
  • Added Priority Flow Control Section
  • Added Physical interface for UltraScale Family devices section
  • Updated Table 2-11, Table 2-13, Table 2-15, Table 2-17, Table 2-34, Table 2-38, Table 2-42, Table 2-43, Table 2-49, Table 2-80 and Table 2-81
12/18/2013 Version 8.1
Product Specification
  • Added UltraScale architecture support
  • Updated Table 2-22, Table 2-24, and Table 2-76.
  • Updated Shared Logic
  • Updated Clocking
Designing with the Core
  • Updated Constraining the Core with description of a new example design file
  • Updated IDELAYCTRL with UltraScale related information
  • Updated Regional Clocking Errors with Vivado error messages
10/02/2013 Version 8.0
Designing with the Core
  • Added Shared Logic section
  • Added IDELAYCTRL information
  • Updated Clock Resource Sharing information
06/19/2013 Version 7.0
Product Specification
  • Revision number advanced to 7.0 to align with core version number.
  • Updated s_axi_awaddr[31:0] and s_axi_araddr[31:0] descriptions in Table 2-12 Optional AXI4-Lite Signal Pinout.
  • Updated Frame Filter Enable (0x70C) to Bits[31:1].
Designing with the Core Updated Figs. 3-5 to 3-6.
Design Flow Steps
  • Updated GUIs in Figs. 4-1 and 4-2.
  • Added descriptions in AXI4-Lite Control State Machine section.
  • Added descriptions in Test Bench Functionality section.
  • Added DEMO Mode with Frame Filter descriptions.
  • Added Changing Frame Data descriptions.
  • TX/RX clock port changes.
  • AXI4-Lite address bus width shrinkage.
  • demo_tb enhancement to illustrate frame filtering.
03/20/2013 Version 2.1
Product Specification
  • Updated to v6.0 for Vivado Design Suite only. Removed .
  • Updated Device Utilization tables (Table 2-1 to 2-4).
  • Updated descriptions in Port Descriptions.
  • tx_enable, rx_enable, speedis10100 and speedis100 outputs now present for all parameterizations
  • tx_axis_mac_tuser is now defined as std_logic_vector for all VHDL parameterizations
Design Flow Steps
  • Updated Figs. 4-1 and 4-2 GUIs
  • Updated AXI4-Lite Control State Machine in Example Design chapter.
  • Added Artix 7 AC701 board support in Example Design chapter.
  • Updated to Questa Advanced Simulator.
12/18/2012 Version 2.0
Designing with the Core
  • Updated to v5.5, Design Suite 14.4/Vivado Design Suite 2012.4.
  • Removed Windows and Linux references in System Requirements.
  • Added note on IEEE 1588 timestamping
  • Updated to 6 cycles in Frame Collisions – Half Duplex Operation section
  • Updated “bytes of transmit data” to Interframe Gap Adjustment Full-Duplex section
  • Updated GMII and RGMII subsections with 7 series in 1 Gbps Ethernet MAC IP Core and Tri-Speed (10 Mbps, 100 Mbps, and 1 Gbps) Ethernet MAC IP Core sections
Design Flow Steps Updated GUI in Fig. 4-1
Test Bench Updated State Machine Flow Diagram in Fig. 6-5
Upgrading Updated GUI in Fig. 7-1
Debugging Updated Debug section and minor document updates.
07/25/2012 Version 1.0
Initial Xilinx release. This Product Guide is derived from DS818 and UG777.