The ports in the following table are only available when using RGMII in AMD Artix™ 7 or AMD Kintex™ 7 devices (see RGMII for 7 Series Devices), and only when the Shared Logic option is selected with the “Include shared logic in core” option.
| Port Name and Width | Direction | Description | What to do |
|---|---|---|---|
| gtx_clk_out | Output | This clock has a 0o phase shift with respect to the gtx_clk input and is used for RGMII data transmission. | This output clock can be used by other TEMAC core instances when sharing clocking resources. See Figure 1 or Figure 2 for a connection illustration. |
| gtx_clk90_out | Output | This clock has a 90o phase shift with respect to the gtx_clk input and is used for RGMII transmitter clock forwarding. | This output clock can be used by other TEMAC core instances when sharing clocking resources. See Figure 1 or Figure 2 for a connection illustration. |