7 Series Devices - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

Document ID
Release Date
9.0 English

When the core is generated with either an RGMII or GMII interface, the core uses IODELAY elements to align the clock and data of the external ports. An IDELAYCTRL must be always used with IODELAYs.

  • If the core is generated using the Shared Logic option, this IDELAYCTRL is present in the core.
  • If the core is generated without the Shared Logic option, an IDELAYCTRL must be instantiated somewhere in the user design. In this case, XDC constraints must be provided to associate the IODELAYs in the core to the instantiated IDELAYCTRL. This is achieved using the “set_property IODELAY_GROUP <name_string>” constraint (see the Vivado Design Suite User Guide: Using Constraints (UG903) ). The core uses the <name_String>tri_mode_ethernet_mac_iodelay_grp for its IODELAY elements for both GMII and RGMII permutations. IDELAYCTRL is always instantiated in the core for UltraScale devices when needed. The XDC constraint associates the IODELAYs with the IDELAYCTRL.