Example Design - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

This section provides detailed information about the example design, including a description of the file groups, contents of the example HDL wrappers, and the operation of the demonstration test bench.

The example design, under certain core configurations, is intended to directly target key AMD Demonstration Families. The currently supported boards are the AMD Kintex™ 7 (KC705 Board) and AMD Artix™ 7 (AC701 Board) FPGAs.

The example design includes a basic state machine which brings up the external PHY and MAC to allow basic frame transfer through the AXI4-Lite interface.

A Simple Frame Generator and Frame Checker are also included which can be used to turn a particular board into a packet generator with any received data optionally being checked. If the TEMAC is generated with the Optional AVB Endpoint another frame generator and frame checker are included to exercise the additional AV datapath.

Loopback functionality is provided as either MAC RX to TX loopback, where the loopback logic becomes the packet source in place of the packet generator, or PHY TX to RX loopback, with the loopback replacing the demonstration test bench stimulus and checker. At present, the loopback logic is not available for the 2.5 Gbps rates. Basic control of the state machine, allowing MAC speed change is achieved using push buttons and DIP switches on the board. See the board specific sections in Targeting the Example Design to a Board.

The following figure illustrates the top-level design for the TEMAC solution example design.

Figure 1. HDL Example Design

The HDL example design contains the following:

  • An instance of the TEMAC solution.
  • Clock management logic including MMCM and Global Clock Buffer instances, where required.
  • MII, GMII, or RGMII interface logic including IOB and DDR registers instances, where required.
  • Statistics vector decode logic.
  • AXI4-Lite to IPIF interface logic.
  • User Transmit and Receive FIFOs with AXI4-Stream interfaces.
  • User basic pattern generator module that contains a frame generator and frame checker plus loopback logic. At present, the loopback logic is not available for 2.5G rates.
  • User AVB pattern generator module providing a second frame generator and frame checker for designs including the AVB Endpoint.
  • A simple state machine to bring up the PHY (if any) and MAC ready for frame transfer

The HDL example design provides basic loopback functionality on the user side of the TEMAC solution and connects the GMII/RGMII interface to external IOBs. It can also operate as a pattern generator with data being optionally looped back externally, on the PHY side, and automatically checked.

This allows the functionality of the core to be demonstrated either using a simulation package, as discussed in this guide, or in hardware if placed on a suitable board. The simple state machine assumes a standard PHY address and registers content as per standard AMD demonstration boards.