The TEMAC solution has a variable number of clocks with the precise number required being dependent upon the specific parameterization.
As the core targets a specific interface standard (RGMII/GMII or MII) there are associated clock frequency requirements.
| Clock Name | Parameterization |
Frequency Requirement (MHz) |
|---|---|---|
| gtx_clk | Always present except when core is configured in MII mode and Statistics counters feature is not enabled. |
125 (at 1 Gbps) 312.5 (at 2.5 Gbps) |
| gtx_clk90 | RGMII when HRIO used for interface. 90° shifted version of gtx_clk | 125 |
| gtx_clk_out | RGMII when HRIO used for interface. Only present when core generated with “Shared logic in core” option. | 125 |
| gtx_clk90_out | RGMII when HRIO used for interface. Only present when core generated with “Shared logic in core” option. | 125 |
| rx_usr_clk2 | Internal mode and Internal Mode Clock Source set to RX User Clk2. Clocks the RX datapath. | 125 |
| refclk | RGMII or GMII. Required for the idelayctrl. For UltraScale architecture-based devices the range is 300–1333 MHz. | 200-300 |
| mii_tx_clk | GMII or MII. Required for 10/100 Mbps operation |
25 (at 100 Mbps) 2.5 (at 10 Mbps) |
| mii_rx_clk | MII |
25 (at 100 Mbps) 2.5 (at 10 Mbps) |
| gmii_rx_clk | GMII |
125 (at 1 Gbps) 25 (at 100 Mbps) 2.5 (at 10 Mbps) |
| rgmii_rxc | RGMII |
125 (at 1 Gbps) 25 (at 100 Mbps) 2.5 (at 10 Mbps) |
| s_axi_aclk | Management Type set to AXI4-Lite | 10-300 |