Transmit Path Latency - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The transmit path latency is measured by counting the number of valid cycles between a data byte being placed on the user interface (tx_axis_mac_tdata ), and it is appearing at the GMII/MII output (gmii_txd ) of the Ethernet MAC core level. So latency values do not include any GMII/MII or RGMII logic within the example design. Transmitter path latency has been measured as:

  • 8 clock-enabled cycles at 1 Gbps or 2.5 Gbps Ethernet speed.
  • 7 or 7.5 clock-enabled cycles at 10 Mbps and 100 Mbps Ethernet speeds. This extra half cycle of uncertainty is due to the conversion of 8-bit user data to 4-bit MII width conversion. Data is presented to the MII at the earliest possible opportunity.